This invention relates generally to level-shifting circuitry.
As is known in the art, level-shifting circuitry is used to shift lower voltage signal levels to higher voltage signal levels. One example of such circuit is shown in FIG. 1. Such circuit is formed on a semiconductor chip and includes a pair of N type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) N1 and N2 and a pair of P type MOSFETs P1 P2 arranged as shown. The P type MOSFETs have the bulk silicon connected to an external +2.5 volt power source. The N type MOSFETs have the bulk silicon connected to ground. The N type MOSFET N1 is a low threshold voltage transistor having. The gate of transistor N1 is connected to an internal +2.1 volt source. The input voltage (IN) is a logic signal having logic 1, here represented by +2.1 volts or a logic 0 state, here represented by ground potential. Here, the level-shifter also provides an inversion in the logic state of the input signal as well as shifting the input signal logic 1 state from +2.1 volts to a higher voltage output signal logic 1 state, here +2.5 volts. Thus, in operation, when the input voltage is logic 0, transistors N1, and P2 are xe2x80x9conxe2x80x9d and transistors P1 and N2 are xe2x80x9coffxe2x80x9d, thereby providing a logic 1, here a +2.5 volt level, at the output OUT. Thus, the input logic 1 condition of a +2.1 volt input signal has been shifted to a +2.5 volt output logic 1. On the other hand, when the input voltage IN is logic 1 (i.e., here +2.1 volts), transistors N1, and P2 are xe2x80x9coffxe2x80x9d and transistors P1 and N2 are xe2x80x9conxe2x80x9d, thereby providing ground potential (i.e., an output logic 0) at the output OUT.
In accordance with the present invention, level-shifting circuitry is provided having a level-shifting section responsive to an input logic signal. The input logic signal has a first voltage level representative of a first logic state or a second voltage level representative of a second logic state. The level-shifting section provides an output logic signal having a third voltage level representative of the first logic state of the input logic signal. The level-shifting circuitry also includes an enable/disable section responsive to an enable/disable signal for driving the output logic signal to a predetermined voltage level during a disable mode.
In one embodiment, the level-shifting section includes: an input transistor having a control electrode, a first electrode coupled to the input logic signal, and a second electrode. An output pair of serially coupled complementary type transistors is provided. A first one of the pair of transistors has a first electrode coupled to a source of the third voltage level and a control electrode coupled to the second electrode of the input transistor. (it should be noted that in the case of a FET, the terms first and second electrode refer to source and drain electrodes, it being understood that while each transistor has a source and drain electrode, the terms may be used interchangeable. Further, in the case of a FET, the term control electrode refers to the gate electrode). A junction between the output pair of transistors provides an output terminal for the level-shifting circuitry. A control electrode of the second one of the pair of transistors is connected to the first electrode of the input transistor.
In one embodiment, the level-shifting section includes an additional transistor. The additional transistor has a control electrode connected to the junction, a first electrode coupled to the source of the third voltage level and a second electrode connected to the second electrode of the input transistor. In one embodiment, the input transistor and the additional transistor are of opposite conductivity type.
In one embodiment, the enable/disable circuit includes a gating transistor having a first electrode connected to the junction and a second electrode connected to the second electrode of the second one of the pair of transistors. An inverter is included coupled between the first electrode of the input transistor and a control electrode of the gating transistor.
In one embodiment, a switch is responsive to the enable/disable signal for preventing current to the additional transistor when in the disable mode.
In one embodiment, the switch is responsive to an output of the inverter and is coupled between the source of the third voltage level and: (1) the output terminal; (2) the first electrode of the additional transistor; and, (3) the first electrode of the first one of the pair of transistors.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.